The present invention relates to a non-volatile programmable integrated memory cell.
A nonvolatile, programmable integrated semiconductor memory cell containing a reading (sensing) FET with a floating gate at normal supply voltage is known from the technical journal "IEEE Transactions on Electron Devices" Vol. ED-24, No. 5 (May 1977), pp. 594 to 599. In this conventional type of semiconductor memory cell, the gate electrode, which has a square configuration, extends beyond the gate surface of the reading IGFET and is capacitatively coupled via two surface portions of insulated-gate parts having a thickness permitting the crossing of the junction by hot carriers, to two programming electrodes, namely, one writing electrode and one erasing electrode, which are formed by planar regions of one conductivity type in a semiconducting substrate of the other conductivity type. The programming electrodes form p.sup.+ -n or n.sup.+ -p junctions, with the p.sup.+ -n junction injecting hot holes, and the n.sup.+ -p junction injecting hot electrons into the adjacent insulated-gate portions of the insulated-gate layer as soon as the breakdown voltage of one of the junctions is exceeded and an avalanche breakdown is initiated. When the insulated-gate portions adjoining the programming electrodes are suitably thin, a small fraction of the hot charge carriers tunnels through the insulated-gate portions and charges or discharges the floating potential gate electrode. The insulated-gate portions of the insulated gate layer which can be tunnelled by the hot charge carriers are restricted in the above-mentioned conventional memory cell to a narrow band adjacent to the punch-through line of the p.sup.+ -n or n.sup.+ -p junction, at the interface semiconductor substrate-insulated-gate layer. The involved insulated-gate portions of the insulated gate layer, therefore, are relatively quickly damaged so that only a relatively low number of programming cycles can be accomplished without causing any substantial damage.